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november 2009 rev 10 1/70 1 m25px64 64-mbit, dual i/o, 4-kbyte subsector erase, serial flash memory with 75 mhz spi bus interface features ? spi bus compatible serial interface ? 75 mhz (maximum) clock frequency ? 2.7 v to 3.6 v single supply voltage ? dual input/output instructions resulting in an equivalent clock frequency of 150 mhz: ? dual output fast read instruction ? dual input fast program instruction ? whole memory continuously read by sending once a fast read or a dual output fast read instruction and an address ? 64 mbit flash memory ? uniform 4-kbyte subsectors ? uniform 64-kbyte sectors ? additional 64-byte user-lockable, one-time programmable (otp) area ? erase capability ? subsector (4-kbyte) granularity ? sector (64-kbyte) granularity ? bulk erase (64 mbits) in 68 s (typical) ? write protections ? software write protection applicable to every 64-kbyte sector (volatile lock bit) ? hardware write protection: protected area size defined by three non-volatile bits (bp0, bp1 and bp2) ? deep power-down mode: 5 a (typical) ? electronic signature ? jedec standard two-byte signature (7117h) ? unique id code (uid) with 16 bytes read- only, available upon customer request ? more than 100 000 write cycles per sector ? more than 20 years data retention ? packages ? rohs compliant ? automotive certified parts available vdfpn8 (me) 8 6 mm (mlp8) so16 (mf) 300 mils width tbga24 (zm) 6x8 mm vdfpn8 (md) 8 6 mm (mlp8) (with reduced d2 dimension) www.numonyx.com
contents m25px64 2/70 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 serial data output (dq1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 serial data input (dq0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 serial clock (c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 chip select (s ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.5 hold (hold ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6 write protect/enhanced program supply voltage (w /v pp ) . . . . . . . . . . . . 10 2.7 v cc supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.8 v ss ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 spi modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1 page programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.2 dual input fast program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.3 subsector erase, sector erase and bulk erase . . . . . . . . . . . . . . . . . . . . . 13 4.4 polling during a write, program or erase cycle . . . . . . . . . . . . . . . . . . . . . 13 4.5 active power, standby power and deep power-down modes . . . . . . . . . . 13 4.6 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.7 protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.7.1 protocol-related protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.7.2 specific hardware and software protection . . . . . . . . . . . . . . . . . . . . . . 16 4.8 hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.1 write enable (wren) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.2 write disable (wrdi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.3 read identification (rdid) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
m25px64 contents 3/70 6.4 read status register (rdsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.4.1 wip bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.4.2 wel bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.4.3 bp2, bp1, bp0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.4.4 top/bottom bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.4.5 srwd bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.5 write status register (wrsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.6 read data bytes (read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.7 read data bytes at higher speed (fast_read) . . . . . . . . . . . . . . . . . . . 37 6.8 dual output fast read (dofr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.9 read lock register (rdlr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.10 read otp (rotp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.11 page program (pp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.12 dual input fast program (difp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6.13 program otp instruction (potp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.14 write to lock register (wrlr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.15 subsector erase (sse) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.16 sector erase (se) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.17 bulk erase (be) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.18 deep power-down (dp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.19 release from deep power-down (rdp) . . . . . . . . . . . . . . . . . . . . . . . . . . 52 7 power-up and power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 8 initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 10 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 11 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 12 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 13 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
list of tables m25px64 4/70 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 2. software protection truth table (sectors 0 to 127, 64-kbyte granularity). . . . . . . . . . . . . . . 16 table 3. protected area sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 4. memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 5. instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 6. read identification (rdid) data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 7. status register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 8. protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 9. lock register out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 10. lock register in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 11. power-up timing and vwi threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 table 12. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 13. operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 14. data retention and endurance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 15. ac measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 16. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 17. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 18. ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 19. vdfpn8 (mlp8, me) 8-lead very thin dual flat package no lead, 8 6 mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 20. vdfpn8 (mlp8, md) 8-lead very thin dual flat package no lead, 8 6 mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 21. so16 wide - 16-lead plastic small outline, 300 mils body width, mechanical data . . . . . . . 64 table 22. tbga 6x8 mm 24-ball package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 23. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 24. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
m25px64 list of figures 5/70 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 2. vdfpn8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. so16 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4. bga 6x8 24 ball ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 5. bus master and memory devices on the spi bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 6. spi modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 7. hold condition activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 8. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 9. write enable (wren) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 10. write disable (wrdi) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 11. read identification (rdid) instruction sequence and data-out sequence . . . . . . . . . . . . . 31 figure 12. read status register (rdsr) instruction sequence and data-out sequence . . . . . . . . . . . 33 figure 13. write status register (wrsr) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 14. read data bytes (read) instruction sequence and data-out sequence . . . . . . . . . . . . . . 36 figure 15. read data bytes at higher speed (fast_read) instruction sequence and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 16. dual output fast read instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 17. read lock register (rdlr) instruction sequence and data-out sequence . . . . . . . . . . . . . 39 figure 18. read otp (rotp) instruction and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 19. page program (pp) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 20. dual input fast program (difp) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 21. program otp (potp) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 22. how to permanently lock the 64 otp bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 23. write to lock register (wrlr) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 24. subsector erase (sse) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 25. sector erase (se) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 9 figure 26. bulk erase (be) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 27. deep power-down (dp) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 28. release from deep power-down (rdp) instruction sequence . . . . . . . . . . . . . . . . . . . . . . 52 figure 29. power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 30. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 31. serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 32. write protect setup and hold timing during wrsr when srwd=1 . . . . . . . . . . . . . . . . . . 60 figure 33. hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 34. output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 35. v pph timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 36. vdfpn8 (mlp8, me) 8-lead very thin dual flat package no lead, 8 6 mm, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 37. vdfpn8 (mlp8, md) 8-lead very thin dual flat package no lead, 8 6 mm, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 38. so16 wide - 16-lead plastic small outline, 300 mils body width, package outline . . . . . . . 64 figure 39. tbga, 6x8 mm, 24 ball package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
description m25px64 6/70 1 description the m25px64 is a 64-mbit (8 mbits x 8) serial flash memory, with advanced write protection mechanisms, accessed by a high speed spi-compatible bus. the m25px64 supports two new, high-performance dual input/output instructions: ? dual output fast read (dofr) instruction used to read data at up to 75 mhz by using both pin dq1 and pin dq0 as outputs ? dual input fast program (difp) instruction used to program data at up to 75 mhz by using both pin dq1 and pin dq0 as inputs these new instructions double the transfer bandwidth for read and program operations. the memory can be programmed 1 to 256 bytes at a time, using the page program instruction. the memory is organized as 128 sectors that are further divided into 16 subsectors each (2048 subsectors in total). the memory can be erased a 4-kbyte subsector at a time, a 64-kbyte sector at a time, or as a whole. it can be write protected by software using a mix of volatile and non-volatile protection features, depending on the application needs. the protection granularity is of 64 kbytes (sector granularity). the m25px64 has 64 one-time-programmable bytes (otp bytes) that can be read and programmed using two dedicated instructions, read otp (rotp) and program otp (potp), respectively. these 64 bytes can be permanently locked by a particular program otp (potp) sequence. once they have been locked, they become read-only and this state cannot be reverted. further features are available as additional security options. more information on these security features is available, upon completion of an nda (nondisclosure agreement), and are, therefore, not described in this datasheet. for more details of this option contact your nearest numonyx sales office.
m25px64 description 7/70 figure 1. logic diagram figure 2. vdfpn8 connections 1. there is an exposed central pad on the underside of the vdfpn8 package. this is pulled, internally, to v ss , and must not be allowed to be connected to any other voltage or signal line on the pcb. 2. see package mechanical section for package dimensions, and how to identify pin-1. table 1. signal names signal name function direction c serial clock input dq0 serial data input i/o (1) 1. serves as an output during dual output fast read (dofr) instructions. dq1 serial data output i/o (2) 2. serves as an input during dual input fast program (difp) instructions. s chip select input w /v pp write protect/enhanced program supply voltage input hold hold input v cc supply voltage ? v ss ground ? ai14228b s v cc m25px64 hold v ss dq1 c dq0 w/v pp 1 ai13720c 2 3 4 8 7 6 5 dq0 v ss c hold dq1 sv cc m25px64 w/v pp
description m25px64 8/70 figure 3. so16 connections 1. du = don?t use. 2. see package mechanical section for package dimensions, and how to identify pin-1. figure 4. bga 6x8 24 ball ballout note: 1 nc = no connection 2see section 11: package mechanical . 1 ai13721c 2 3 4 16 15 14 13 du du du du v cc hold du du m25px64 5 6 7 8 12 11 10 9 dq1 v ss du du s dq0 c w/v pp
m25px64 signal descriptions 9/70 2 signal descriptions 2.1 serial data output (dq1) this output signal is used to transfer data serially out of the device. data are shifted out on the falling edge of serial clock (c). during the dual input fast program (difp) instruction, pin dq1 is used as an input. it is latched on the rising edge of the serial clock (c). 2.2 serial data input (dq0) this input signal is used to transfer data serially into the device. it receives instructions, addresses, and the data to be programmed. values are latched on the rising edge of serial clock (c). during the dual output fast read (dofr) instruction, pin dq0 is used as an output. data are shifted out on the falling edge of the serial clock (c). 2.3 serial clock (c) this input signal provides the timing of the serial interface. instructions, addresses, or data present at serial data input (dq0) are latched on the rising edge of serial clock (c). data on serial data output (dq1) changes after the falling edge of serial clock (c). 2.4 chip select (s ) when this input signal is high, the device is deselected and serial data output (dq1) is at high impedance. unless an internal program, erase or write status register cycle is in progress, the device will be in the standby power mode (this is not the deep power-down mode). driving chip select (s ) low enables the device, placing it in the active power mode. after power-up, a falling edge on chip select (s ) is required prior to the start of any instruction. 2.5 hold (hold ) the hold (hold ) signal is used to pause any serial communications with the device without deselecting the device. during the hold condition, the serial data output (dq1) is high impedance, and serial data input (dq0) and serial clock (c) are don?t care. to start the hold condition, the device must be selected, with chip select (s ) driven low.
signal descriptions m25px64 10/70 2.6 write protect/enhanced program supply voltage (w /v pp ) w /v pp is both a control input and a power supply pin. the two functions are selected by the voltage range applied to the pin. if the w /v pp input is kept in a low voltage range (0 v to v cc ) the pin is seen as a control input. this input signal is used to freeze the size of the area of memory that is protected against program or erase instructions (as specified by the values in the bp2, bp1 and bp0 bits of the status register. see ta bl e 9 ). if v pp is in the range of v pph (as defined in table 15 ) it acts as an additional power supply. (1) 2.7 v cc supply voltage v cc is the supply voltage. 2.8 v ss ground v ss is the reference for the v cc supply voltage. 1. avoid applying v pph to the w /vpp pin during bulk erase.
m25px64 spi modes 11/70 3 spi modes these devices can be driven by a microcontroller with its spi peripheral running in either of the two following modes: ? cpol=0, cpha=0 ? cpol=1, cpha=1 for these two modes, input data is latched in on the rising edge of serial clock (c), and output data is available from the falling edge of serial clock (c). the difference between the two modes, as shown in figure 6 , is the clock polarity when the bus master is in standby mode and not transferring data: ? c remains at 0 for (cpol=0, cpha=0) ? c remains at 1 for (cpol=1, cpha=1) figure 5. bus master and memory devices on the spi bus 1. the write protect (w ) and hold (hold ) signals should be driven, high or low as appropriate. figure 5 shows an example of three devices connected to an mcu, on an spi bus. only one device is selected at a time, so only one device drives the serial data output (dq1) line at a time, the other devices are high impedance. resistors r (represented in figure 5 ) ensure that the m25px64 is not selected if the bus master leaves the s line in the high impedance state. as the bus master may enter a state where all inputs/outputs are in high impedance at the same time (for example, when the bus master is reset), the clock line (c) must be connected to an external pull-down resistor so that, when all inputs/outputs become high impedance, the s line is pulled high while the c line is pulled low (thus ensuring that s and c do not become high at the same time, and so, that the t shch requirement is met). the typical value of r is 100 k , assuming that the time constant r*c p (c p = parasitic capacitance of the bus line) is shorter than the time during which the bus master leaves the spi bus in high impedance. ai13725b spi bus master spi memory device sdo sdi sck c dq1dq0 s spi memory device c dq1 dq0 s spi memory device c dq1dq0 s cs3 cs2 cs1 spi interface with (cpol, cpha) = (0, 0) or (1, 1) w hold hold w hold rrr v cc v cc v cc v cc v ss v ss v ss v ss r w
spi modes m25px64 12/70 example: c p = 50 pf, that is r*c p = 5 s <=> the application must ensure that the bus master never leaves the spi bus in the high impedance state for a time period shorter than 5 s. figure 6. spi modes supported ai1373 0 c msb cpha dq0 0 1 cpol 0 1 dq1 c msb
m25px64 operating features 13/70 4 operating features 4.1 page programming to program one data byte, two instructions are required: write enable (wren), which is one byte, and a page program (pp) sequence, which consists of four bytes plus data. this is followed by the internal program cycle (of duration t pp ). to spread this overhead, the page program (pp) instruction allows up to 256 bytes to be programmed at a time (changing bits from ?1? to ?0?), provided that they lie in consecutive addresses on the same page of memory. for optimized timings, it is recommended to use the page program (pp) instruction to program all consecutive targeted bytes in a single sequence versus using several page program (pp) sequences with each containing only a few bytes (see page program (pp) and table 18: ac characteristics ). 4.2 dual input fast program the dual input fast program (difp) instruction makes it possible to program up to 256 bytes using two input pins at the same time (by changing bits from ?1? to ?0?). for optimized timings, it is recommended to use the dual input fast program (difp) instruction to program all consecutive targeted bytes in a single sequence rather to using several dual input fast program (difp) sequences each containing only a few bytes (see section 6.12: dual input fast program (difp) ). 4.3 subsector erase, sector erase and bulk erase the page program (pp) instruction allows bits to be reset from ?1? to ?0?. before this can be applied, the bytes of memory need to have been erased to all 1s (ffh). this can be achieved either a subsector at a time, using the subsector erase (sse) instruction, a sector at a time, using the sector erase (se) instruction, or throughout the entire memory, using the bulk erase (be) instruction. this starts an internal erase cycle (of duration t sse , t se or t be ). the erase instruction must be preceded by a write enable (wren) instruction. 4.4 polling during a write, program or erase cycle a further improvement in the time to write status register (wrsr), program otp (potp), program (pp), dual input fast program (difp) or erase (sse, se or be) can be achieved by not waiting for the worst case delay (t w , t pp , t sse , t se , or t be ). the write in progress (wip) bit is provided in the status register so that the application program can monitor its value, polling it to establish when the previous write cycle, program cycle or erase cycle is complete. 4.5 active power, standby power and deep power-down modes when chip select (s ) is low, the device is selected, and in the active power mode.
operating features m25px64 14/70 when chip select (s ) is high, the device is deselected, but could remain in the active power mode until all internal cycles have completed (program, erase, write status register). the device then goes in to the standby power mode. the device consumption drops to i cc1 . the deep power-down mode is entered when the specific instruction (the deep power-down (dp) instruction) is executed. the device consumption drops further to i cc2 . the device remains in this mode until another specific instruction (the release from deep power-down (rdp) instruction) is executed. while in the deep power-down mode, the device ignores all write, program and erase instructions (see section 6.18: deep power-down (dp) ), this can be used as an extra software protection mechanism, when the device is not in active use, to protect the device from inadvertent write, program or erase instructions. 4.6 status register the status register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions. see section 6.4: read status register (rdsr) for a detailed description of the status register bits.
m25px64 operating features 15/70 4.7 protection modes there are protocol-related and specific hardware and software protection modes. they are described below. 4.7.1 protocol-related protections the environments where non-volatile memory devices are used can be very noisy. no spi device can operate correctly in the presence of excessive noise. to help combat this, the m25px64 features the following data protection mechanisms: ? power on reset and an internal timer (t puw ) can provide protection against inadvertent changes while the power supply is outside the operating specification ? program, erase and write status register instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution ? all instructions that modify data must be preceded by a write enable (wren) instruction to set the write enable latch (wel) bit. this bit is returned to its reset state by the following events: ? power-up ? write disable (wrdi) instruction completion ? write status register (wrsr) instruction completion ? write to lock register (wrlr) instruction completion ? program otp (potp) instruction completion ? page program (pp) instruction completion ? dual input fast program (difp) instruction completion ? subsector erase (sse) instruction completion ? sector erase (se) instruction completion ? bulk erase (be) instruction completion ? in addition to the low power consumption feature, the deep power-down mode offers extra software protection, as all write, program and erase instructions are ignored.
operating features m25px64 16/70 4.7.2 specific hardware and software protection there are two software protected modes, spm1 and spm2, that can be combined to protect the memory array as required. the spm2 can be locked by hardware with the help of the w input pin. spm1 and spm2 ? the first software protected mode (spm1) is managed by specific lock registers assigned to each 64-kbyte sector. the lock registers can be read and written using the read lock register (rdlr) and write to lock register (wrlr) instructions. in each lock register two bits control the protection of each sector: the write lock bit and the lock down bit. ? write lock bit: the write lock bit determines whether the contents of the sector can be modified (using the write, program or erase instructions). when the write lock bit is set to ?1?, the sector is write protected ? any operations that attempt to change the data in the sector will fail. when the write lock bit is reset to ?0?, the sector is not write protected by the lock register, and may be modified. ? lock down bit: the lock down bit provides a mechanism for protecting software data from simple hacking and malicious attack. when the lock down bit is set to ?1?, further modification to the write lock and lock down bits cannot be performed. a power-up is required before changes to these bits can be made. when the lock down bit is reset to ?0?, the write lock and lock down bits can be changed. the definition of the lock register bits is given in table 9: lock register out . ? the second software protected mode (spm2) uses the block protect bits (see section 6.4.3: bp2, bp1, bp0 bits ) and the top/bottom bit (see section 6.4.4: top/bottom bit ) to allow part of the memory to be configured as read-only. table 2. software protection truth table (sectors 0 to 127, 64-kbyte granularity) sector lock register protection status lock down bit write lock bit 00 sector unprotected from program/erase/write operations, protection status reversible 01 sector protected from program/erase/write operations, protection status reversible 10 sector unprotected from program/erase/write operations, sector protection status cannot be changed except by a power-up. 11 sector protected from program/erase/write operations, sector protection status cannot be changed except by a power-up.
m25px64 operating features 17/70 as a second level of protection, the write protect signal (applied on the w /v pp pin) can freeze the status register in a read-only mode. in this mode, the block protect bits (bp2, bp1, bp0) and the status register write disable bit (srwd) are protected. for more details, see section 6.5: write status register (wrsr) . table 3. protected area sizes status register contents memory content tb bit bp bit 2 bp bit 1 bp bit 0 protected area unprotected area 0 0 0 0 none all sectors (1) (128 sectors: 0 to 127) 0 0 0 1 upper 64th (2 sectors: 126 and 127) lower 63/64ths (126 sectors: 0 to 125) 0 0 1 0 upper 32nd (4 sectors: 124 to 127) lower 31/32nds (124 sectors: 0 to 123) 0 0 1 1 upper 16th (8 sectors: 120 to 127) lower 15/16ths (120 sectors: 0 to 119) 0 1 0 0 upper 8th (16 sectors: 56 to 63) lower 7/8ths (112 sectors: 0 to 111) 0 1 0 1 upper quarter (32 sectors: 96 to 127) lower three-quarters (96 sectors: 0 to 95) 0 1 1 0 upper half (64 sectors: 64 to 127) lower half (64 sectors: 0 to 63) 0 1 1 1 all sectors (128 sectors: 0 to 127) none 1 0 0 0 none all sectors (1) (128 sectors: 0 to 128) 1 0 0 1 lower 64th (2 sectors: 0 to1) upper 63/64ths (126 sectors: 2 to 127) 1 0 1 0 lower 32nd (4 sectors: 0 to 3) upper 31/32nds (124 sectors: 4 to 127) 1 0 1 1 lower 16th (8 sectors: 0 to 7) upper 15/16ths (120 sectors: 8 to 127) 1 1 0 0 lower 8th (16 sectors: 0 to15) upper 7/8ths (112 sectors: 16 to 127) 1 1 0 1 lower 4th (32 sectors: 0 to 31) upper 3/4ths (96 sectors: 32 to 127) 1 1 1 0 lower half (64 sectors: 0 to 63) upper half (64 sectors: 64 to 127) 1 1 1 1 all sectors (128 sectors: 0 to 127) none 1. the device is ready to accept a bulk erase instruction if, and only if, all block protect (bp2, bp1, bp0) are 0.
operating features m25px64 18/70 4.8 hold condition the hold (hold ) signal is used to pause any serial communications with the device without resetting the clocking sequence. however, taking this signal low does not terminate any write status register, program or erase cycle that is currently in progress. to enter the hold condition, the device must be selected, with chip select (s ) low. the hold condition starts on the falling edge of the hold (hold ) signal, provided that this coincides with serial clock (c) being low (as shown in figure 7 ). the hold condition ends on the rising edge of the hold (hold ) signal, provided that this coincides with serial clock (c) being low. if the falling edge does not coincide with serial clock (c) being low, the hold condition starts after serial clock (c) next goes low. similarly, if the rising edge does not coincide with serial clock (c) being low, the hold condition ends after serial clock (c) next goes low (this is shown in figure 7 ). during the hold condition, the serial data output (dq1) is high impedance, and serial data input (dq0) and serial clock (c) are don?t care. normally, the device is kept selected, with chip select (s ) driven low, for the whole duration of the hold condition. this is to ensure that the state of the internal logic remains unchanged from the moment of entering the hold condition. if chip select (s ) goes high while the device is in the hold condition, this has the effect of resetting the internal logic of the device. to restart communication with the device, it is necessary to drive hold (hold ) high, and then to drive chip select (s ) low. this prevents the device from going back to the hold condition. figure 7. hold condition activation ai02029d hold c hold condition (standard use) hold condition (non-standard use)
m25px64 memory organization 19/70 5 memory organization the memory is organized as: ? 8 388 608 bytes (8 bits each) ? 2048 subsectors (4 kbytes each) ? 128 sectors (64 kbytes each) ? 32768 pages (256 bytes each) ? 64 otp bytes located outside the main memory array. each page can be individually programmed (bits are programmed from ?1? to ?0?). the device is subsector, sector or bulk erasable (bits are erased from ?0? to ?1?) but not page erasable. figure 8. block diagram ai13722b hold s w/v pp control logic high voltage generator i/o shift register address register and counter 256 byte data buffer 256 bytes (page size) x decoder y decoder c dq0 dq1 status register 00000h 7fffffh 000ffh 64 otp bytes
memory organization m25px64 20/70 table 4. memory organization sector subsector address range sector subsector address range 127 2047 7ff000h 7fffffh 116 1871 74f000h 74ffffh ... ... ... ... ... ... 2032 7f0000h 7f0fffh 1856 740000h 740fffh 126 2031 7ef000h 7effffh 115 1855 73f000h 73ffffh ... ... ... ... ... ... 2016 7e0000h 7e0fffh 1840 730000h 730fffh 125 2015 7df000h 7dffffh 114 1839 72f000h 72ffffh ... ... ... ... ... ... 2000 7d0000h 7d0fffh 1824 720000h 720fffh 124 1999 7cf000h 7cffffh 113 1823 71f000h 71ffffh ... ... ... ... ... ... 1984 7c0000h 7c0fffh 1808 710000h 710fffh 123 1983 7bf000h 7bffffh 112 1807 70f000h 70ffffh ... ... ... ... ... ... 1968 7b0000h 7b0fffh 1792 700000h 700fffh 122 1967 7af000h 7affffh 111 1791 6ff000h 6fffffh ... ... ... ... ... ... 1952 7a0000h 7a0fffh 1776 6f0000h 6f0fffh 121 1951 79f000h 79ffffh 110 1775 6ef000h 6effffh ... ... ... ... ... ... 1936 790000h 790fffh 1760 6e0000h 6e0fffh 120 1935 78f000h 78ffffh 109 1759 6df000h 6dffffh ... ... ... ... ... ... 1920 780000h 780fffh 1744 6d0000h 6d0fffh 119 1919 77f000h 77ffffh 108 1743 6cf000h 6cffffh ... ... ... ... ... ... 1904 770000h 770fffh 1728 6c0000h 6c0fffh 118 1903 76f000h 76ffffh 107 1727 6bf000h 6bffffh ... ... ... ... ... ... 1888 760000h 760fffh 1712 6b0000h 6b0fffh 117 1887 75f000h 75ffffh 106 1711 6af000h 6affffh ... ... ... ... ... ... 1872 750000h 750fffh 1696 6a0000h 6a0fffh
m25px64 memory organization 21/70 105 1695 69f000h 69ffffh 94 1519 5ef000h 5effffh ... ... ... ... ... ... 1680 690000h 690fffh 1504 5e0000h 5e0fffh 104 1679 68f000h 68ffffh 93 1503 5df000h 5dffffh ... ... ... ... ... ... 1664 680000h 680fffh 464 5d0000h 5d0fffh 103 1663 67f000h 67ffffh 92 1487 5cf000h 5cffffh ... ... ... ... ... ... 1648 670000h 670fffh 1472 5c0000h 5c0fffh 102 1647 66f000h 66ffffh 91 1471 5bf000h 5bffffh ... ... ... ... ... ... 1632 660000h 660fffh 1456 5b0000h 5b0fffh 101 1631 65f000h 65ffffh 90 1455 5af000h 5affffh ... ... ... ... ... ... 1616 650000h 650fffh 1440 5a0000h 5a0fffh 100 1615 64f000h 64ffffh 89 1439 59f000h 59ffffh ... ... ... ... ... ... 1600 640000h 640fffh 1424 590000h 590fffh 99 1599 63f000h 63ffffh 88 1423 58f000h 58ffffh ... ... ... ... ... ... 1584 630000h 630fffh 1408 580000h 580fffh 98 1583 62f000h 62ffffh 87 1407 57f000h 57ffffh ... ... ... ... ... ... 1568 620000h 620fffh 1392 570000h 570fffh 97 1567 61f000h 61ffffh 86 1391 56f000h 56ffffh ... ... ... ... ... ... 1552 610000h 610fffh 1376 560000h 560fffh 96 1551 60f000h 60ffffh 85 1375 55f000h 55ffffh ... ... ... ... ... ... 1536 600000h 600fffh 1360 550000h 550fffh 95 1535 5ff000h 5fffffh 84 1359 54f000h 54ffffh ... ... ... ... ... ... 1520 5f0000h 5f0fffh 1344 540000h 540fffh table 4. memory organization (continued) sector subsector address range sector subsector address range
memory organization m25px64 22/70 83 1343 53f000h 53ffffh 72 1167 48f000h 48ffffh ... ... ... ... ... ... 1328 530000h 530fffh 1152 480000h 480fffh 82 1327 52f000h 52ffffh 71 1151 47f000h 47ffffh ... ... ... ... ... ... 1312 520000h 520fffh 1136 470000h 470fffh 81 1311 51f000h 51ffffh 70 1135 46f000h 46ffffh ... ... ... ... ... ... 1296 510000h 510fffh 1120 460000h 460fffh 80 1295 50f000h 50ffffh 69 1119 45f000h 45ffffh ... ... ... ... ... ... 1280 500000h 500fffh 1104 450000h 450fffh 79 1279 4ff000h 4fffffh 68 1103 44f000h 44ffffh ... ... ... ... ... ... 1264 4f0000h 4f0fffh 1088 440000h 440fffh 78 1263 4ef000h 4effffh 67 1087 43f000h 43ffffh ... ... ... ... ... ... 1248 4e0000h 4e0fffh 1072 430000h 430fffh 77 1247 4df000h 4dffffh 66 1071 42f000h 42ffffh ... ... ... ... ... ... 1232 4d0000h 4d0fffh 1056 420000h 420fffh 76 1231 4cf000h 4cffffh 65 1055 41f000h 41ffffh ... ... ... ... ... ... 1216 4c0000h 4c0fffh 1040 410000h 410fffh 75 1215 4bf000h 4bffffh 64 1039 40f000h 40ffffh ... ... ... ... ... ... 1200 4b0000h 4b0fffh 1024 400000h 400fffh 74 1199 4af000h 4affffh 63 1023 3ff000h 3ff000h ... ... ... 1184 4a0000h 4a0fffh 1008 3f0000h 3f0fffh 73 1183 49f000h 49ffffh 62 1007 3ef000h 3effffh ... ... ... ... ... ... 1168 490000h 490fffh 992 3e0000h 3e0fffh table 4. memory organization (continued) sector subsector address range sector subsector address range
m25px64 memory organization 23/70 61 991 3df000h 3dffffh 50 815 32f000h 32ffffh ... ... ... ... ... ... 976 3d0000h 3d0fffh 800 320000h 320fffh 60 975 3cf000h 3cffffh 49 799 31f000h 31ffffh ... ... ... ... ... ... 960 3c0000h 3c0fffh 784 310000h 310fffh 59 959 3bf000h 3bffffh 48 783 30f000h 30ffffh ... ... ... ... ... ... 944 3b0000h 3b0fffh 768 300000h 300fffh 58 943 3af000g 3affffh 47 767 2ff000h 2fffffh ... ... ... ... ... ... 928 3a0000h 3a0fffh 752 2f0000h 2f0fffh 57 927 39f000h 39ffffh 46 751 2ef000h 2effffh ... ... ... ... ... ... 912 390000h 390fffh 736 2e0000h 2e0fffh 56 911 38f000h 38ffffh 45 735 2df000h 2dffffh ... ... ... ... ... ... 896 380000h 380fffh 720 2d0000h 2d0fffh 55 895 37f000h 37ffffh 44 719 2cf000h 2cffffh ... ... ... ... ... ... 880 370000h 370fffh 704 2c0000h 2c0fffh 54 879 36f000h 36ffffh 43 703 2bf000h 2bffffh ... ... ... ... ... ... 864 360000h 360fffh 688 2b0000h 2b0fffh 53 863 35f000h 35ffffh 42 687 2af000h 2affffh ... ... ... ... ... ... 848 350000h 350fffh 672 2a0000h 2a0fffh 52 847 34f000h 34ffffh 41 671 29f000h 29ffffh ... ... ... ... ... ... 832 340000h 340fffh 656 290000h 290fffh 51 831 33f000h 33ffffh 40 655 28f000h 28ffffh ... ... ... ... ... ... 816 330000h 330fffh 640 280000h 280fffh table 4. memory organization (continued) sector subsector address range sector subsector address range
memory organization m25px64 24/70 39 639 27f000h 27ffffh 28 463 1cf000h 1cffffh ... ... ... ... ... ... 624 270000h 270fffh 448 1c0000h 1c0fffh 38 623 26f000h 26ffffh 27 447 1bf000h 1bffffh ... ... ... ... ... ... 608 260000h 260fffh 432 1b0000h 1b0fffh 37 607 25f000h 25ffffh 26 431 1af000h 1affffh ... ... ... ... ... ... 592 250000h 250fffh 416 1a0000h 1a0fffh 36 591 24f000h 24ffffh 25 415 19f000h 19ffffh ... ... ... ... ... ... 576 240000h 240fffh 400 190000h 190fffh 35 575 23f000h 23ffffh 24 399 18f000h 18ffffh ... ... ... ... ... ... 560 230000h 230fffh 384 180000h 180fffh 34 559 22f000h 22ffffh 23 383 17f000h 17ffffh ... ... ... ... ... ... 544 220000h 220fffh 368 170000h 170fffh 33 543 21f000h 21ffffh 22 367 16f000h 16ffffh ... ... ... ... ... ... 528 210000h 210fffh 352 160000h 160fffh 32 527 20f000h 20ffffh 21 351 15f000h 15ffffh ... ... ... ... ... ... 512 200000h 200fffh 336 150000h 150fffh 31 511 1ff000h 1fffffh 20 335 14f000h 14ffffh ... ... ... ... ... ... 496 1f0000h 1f0fffh 320 140000h 140fffh 30 495 1ef000h 1effffh 19 319 13f000h 13ffffh ... ... ... ... ... ... 480 1e0000h 1e0fffh 304 130000h 130fffh 29 479 1df000h 1dffffh 18 303 12f000h 12ffffh ... ... ... ... ... ... 464 1d0000h 1d0fffh 288 120000h 120fffh table 4. memory organization (continued) sector subsector address range sector subsector address range
m25px64 memory organization 25/70 17 287 11f000h 11ffffh 7 127 7f000h 7ffffh ... ... ... ... ... ... 272 110000h 110fffh 112 70000h 70fffh 16 271 10f000h 10ffffh 6 111 6f000h 6ffffh ... ... ... ... ... ... 256 100000h 100fffh 96 60000h 60fffh 15 255 ff000h fffffh 5 95 5f000h 5ffffh ... ... ... ... ... ... 240 f0000h f0fffh 80 50000h 50fffh 14 239 ef000h effffh 4 79 4f000h 4ffffh ... ... ... ... ... ... 224 e0000h e0fffh 64 40000h 40fffh 13 223 df000h dffffh 3 63 3f000h 3ffffh ... ... ... ... ... ... 208 d0000h d0fffh 48 30000h 30fffh 12 207 cf000h cffffh 2 47 2f000h 2ffffh ... ... ... ... ... ... 192 c0000h c0fffh 32 20000h 20fffh 11 191 bf000h bffffh 1 31 1f000h 1ffffh ... ... ... ... ... ... 176 b0000h b0fffh 16 10000h 10fffh 10 175 af000h affffh 0 15 0f000h 0ffffh ... ... ... 160 a0000h a0fffh 4 04000h 04fffh 9 159 9f000h 9ffffh 3 03000h 03fffh ... ... ... 2 02000h 02fffh 144 90000h 90fffh 1 01000h 01fffh 8 143 8f000h 8ffffh 0 00000h 00fffh ... ... ... 128 80000h 80fffh table 4. memory organization (continued) sector subsector address range sector subsector address range
instructions m25px64 26/70 6 instructions all instructions, addresses and data are shifted in and out of the device, most significant bit first. serial data input(s) dq0 (dq1) is (are) sampled on the first rising edge of serial clock (c) after chip select (s ) is driven low. then, the one-byte instruction code must be shifted in to the device, most significant bit first, on serial data input(s) dq0 (dq1), each bit being latched on the rising edges of serial clock (c). the instruction set is listed in ta bl e 5 . every instruction sequence starts with a one-byte instruction code. depending on the instruction, this might be followed by address bytes, or by data bytes, or by both or none. in the case of a read data bytes (read), read data bytes at higher speed (fast_read), dual output fast read (dofr), read otp (rotp), read lock registers (rdlr), read status register (rdsr), read identification (rdid) or release from deep power-down (rdp) instruction, the shifted-in instruction sequence is followed by a data-out sequence. chip select (s ) can be driven high after any bit of the data-out sequence is being shifted out. in the case of a page program (pp), program otp (potp), dual input fast program (difp), subsector erase (sse), sector erase (se), bulk erase (be), write status register (wrsr), write to lock register (wrlr), write enable (wren), write disable (wrdi) or deep power- down (dp) instruction, chip select (s ) must be driven high exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. that is, chip select (s ) must driven high when the number of clock pulses after chip select (s ) being driven low is an exact multiple of eight. all attempts to access the memory array during a write status register cycle, program cycle or erase cycle are ignored, and the internal write status register cycle, program cycle or erase cycle continues unaffected. note: output hi-z is defined as the point where data out is no longer driven.
m25px64 instructions 27/70 table 5. instruction set instruction description one-byte instruction code address bytes dummy bytes data bytes wren write enable 0000 0110 06h 0 0 0 wrdi write disable 0000 0100 04h 0 0 0 rdid read identification 1001 1111 9fh 0 0 1 to 20 1001 1110 9eh 0 0 1 to 3 rdsr read status register 0000 0101 05h 0 0 1 to wrsr write status register 0000 0001 01h 0 0 1 wrlr write to lock register 1110 0101 e5h 3 0 1 rdlr read lock register 1110 1000 e8h 3 0 1 read read data bytes 0000 0011 03h 3 0 1 to fast_read read data bytes at higher speed 0000 1011 0bh 3 1 1 to dofr dual output fast read 0011 1011 3bh 3 1 1 to rotp read otp (read 64 bytes of otp area) 0100 1011 4bh 3 1 1 to 65 potp program otp (program 64 bytes of otp area) 0100 0010 42h 3 0 1 to 65 pp page program 0000 0010 02h 3 0 1 to 256 difp dual input fast program 1010 0010 a2h 3 0 1 to 256 sse subsector erase 0010 0000 20h 3 0 0 se sector erase 1101 1000 d8h 3 0 0 be bulk erase 1100 0111 c7h 0 0 0 dp deep power-down 1011 1001 b9h 0 0 0 rdp release from deep power-down 1010 1011 abh 0 0 0
instructions m25px64 28/70 6.1 write enable (wren) the write enable (wren) instruction ( figure 9 ) sets the write enable latch (wel) bit. the write enable latch (wel) bit must be set prior to every page program (pp), dual input fast program (difp), program otp (potp), write to lock register (wrlr), subsector erase (sse), sector erase (se), bulk erase (be) and write status register (wrsr) instruction. the write enable (wren) instruction is entered by driving chip select (s ) low, sending the instruction code, and then driving chip select (s ) high. figure 9. write enable (wren) instruction sequence c dq0 ai13731 s dq1 2 1 34567 high impedance 0 instruction
m25px64 instructions 29/70 6.2 write disable (wrdi) the write disable (wrdi) instruction ( figure 10 ) resets the write enable latch (wel) bit. the write disable (wrdi) instruction is entered by driving chip select (s ) low, sending the instruction code, and then driving chip select (s ) high. the write enable latch (wel) bit is reset under the following conditions: ? power-up ? write disable (wrdi) instruction completion ? write status register (wrsr) instruction completion ? write to lock register (wrlr) instruction completion ? page program (pp) instruction completion ? dual input fast program (difp) instruction completion ? program otp (potp) instruction completion ? subsector erase (sse) instruction completion ? sector erase (se) instruction completion ? bulk erase (be) instruction completion figure 10. write disable (wrdi) instruction sequence c dq0 ai13732 s dq1 2 1 34567 high impedance 0 instruction
instructions m25px64 30/70 6.3 read identification (rdid) the read identification (rdid) instruction allows to read the device identification data: ? manufacturer identification (1 byte) ? device identification (2 bytes) ? a unique id code (uid) (17 bytes, of which 16 available upon customer request). the manufacturer identification is assigned by jedec, and has the value 20h for numonyx. the device identification is assigned by the device manufacturer, and indicates the memory type in the first byte (71h), and the memory capacity of the device in the second byte (17h). the uid contains the length of the following data in the first byte (set to 10h) and 16 bytes of the optional customized factory data (cfd) content. the cfd bytes are read-only and can be programmed with customers data upon their demand. if the customers do not make requests, the devices are shipped with all the cfd bytes programmed to zero (00h). any read identification (rdid) instruction while an erase or program cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. the read identification (rdid) instruction should not be issued while the device is in deep power-down mode. the device is first selected by driving chip select (s ) low. then, the 8-bit instruction code for the instruction is shifted in. after this, the 24-bit device identification, stored in the memory, the 8-bit cfd length followed by 16 bytes of cfd content will be shifted out on serial data output (dq1). each bit is shifted out during the falling edge of serial clock (c). the instruction sequence is shown in figure 11 . the read identification (rdid) instruction is terminated by driving chip select (s ) high at any time during data output. when chip select (s ) is driven high, the device is put in the standby power mode. once in the standby power mode, the device waits to be selected, so that it can receive, decode and execute instructions. table 6. read identification (rdid) data-out sequence manufacturer identification device identification uid memory type memory capacity cfd length cfd content 20h 71h 17h 10h 16 bytes
m25px64 instructions 31/70 figure 11. read identification (rdid) instruction sequence and data-out sequence c dq0 s 2 13 456789101112131415 instruction 0 ai06809d dq1 manufacturer identification high impedance msb device identification msb 15 14 13 3 2 1 0 16 17 18 28 29 30 31 msb uid
instructions m25px64 32/70 6.4 read status register (rdsr) the read status register (rdsr) instruction allows the status register to be read. the status register may be read at any time, even while a program, erase or write status register cycle is in progress. when one of these cycles is in progress, it is recommended to check the write in progress (wip) bit before sending a new instruction to the device. it is also possible to read the status register continuously, as shown in figure 12 . the status and control bits of the status register are as follows: 6.4.1 wip bit the write in progress (wip) bit indicates whether the memory is busy with a write status register, program or erase cycle. when set to ?1?, such a cycle is in progress, when reset to ?0? no such cycle is in progress. 6.4.2 wel bit the write enable latch (wel) bit indicates the status of the internal write enable latch. when set to ?1? the internal write enable latch is set, when set to ?0? the internal write enable latch is reset and no write status register, program or erase instruction is accepted. 6.4.3 bp2, bp1, bp0 bits the block protect (bp2, bp1, bp0) bits are non-volatile. they define the size of the area to be software protected against program and erase instructions. these bits are written with the write status register (wrsr) instruction. when one or more of the block protect (bp2, bp1, bp0) bits is set to ?1?, the relevant memory area (as defined in ta bl e 3 ) becomes protected against page program (pp) and sector erase (se) instructions. the block protect (bp2, bp1, bp0) bits can be written provided that the hardware protected mode has not been set. the bulk erase (be) instruction is executed if, and only if, all block protect (bp2, bp1, bp0) bits are 0. table 7. status register format b7 b0 srwd 0 tb bp2 bp1 bp0 wel wip status register write protect top/bottom bit block protect bits write enable latch bit write in progress bit
m25px64 instructions 33/70 6.4.4 top/bottom bit the top/bottom (tb) bit is non-volatile. it can be set and reset with the write status register (wrsr) instruction provided that the write enable (wren) instruction has been issued. the top/bottom (tb) bit is used in conjunction with the block protect (bp0, bp1, bp2) bits to determine if the protected area defined by the block protect bits starts from the top or the bottom of the memory array: ? when top/bottom bit is reset to ?0? (default value), the area protected by the block protect bits starts from the top of the memory array (see table 3: protected area sizes ) ? when top/bottom bit is set to ?1?, the area protected by the block protect bits starts from the bottom of the memory array (see table 3: protected area sizes ). the top/bottom bit cannot be written when the srwd bit is set to ?1? and the w pin is driven low. 6.4.5 srwd bit the status register write disable (srwd) bit is operated in conjunction with the write protect (w /v pp ) signal. the status register write disable (srwd) bit and the write protect (w /v pp ) signal allow the device to be put in the hardware protected mode (when the status register write disable (srwd) bit is set to ?1?, and write protect (w /v pp ) is driven low). in this mode, the non-volatile bits of the status register (srwd, bp2, bp1, bp0) become read-only bits and the write status register (wrsr) instruction is no longer accepted for execution. figure 12. read status register (rdsr) instruction sequence and data-out sequence c dq0 s 2 1 3456789101112131415 instruction 0 ai13734 dq1 7 6543210 status register out high impedance msb 7 6543210 status register out msb 7
instructions m25px64 34/70 6.5 write status register (wrsr) the write status register (wrsr) instruction allows new values to be written to the status register. before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been decoded and executed, the device sets the write enable latch (wel). the write status register (wrsr) instruction is entered by driving chip select (s ) low, followed by the instruction code and the data byte on serial data input (dq0). the instruction sequence is shown in figure 13 . the write status register (wrsr) instruction has no effect on b6, b1 and b0 of the status register. b6 is always read as ?0?. chip select (s ) must be driven high after the eighth bit of the data byte has been latched in. if not, the write status register (wrsr) instruction is not executed. as soon as chip select (s ) is driven high, the self-timed write status register cycle (whose duration is t w ) is initiated. while the write status register cycle is in progress, the status register may still be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed write status register cycle, and is 0 when it is completed. when the cycle is completed, the write enable latch (wel) is reset. the write status register (wrsr) instruction allows the user to change the values of the block protect (bp2, bp1, bp0) bits, to define the size of the area that is to be treated as read-only, as defined in table 3 . the write status register (wrsr) instruction also allows the user to set and reset the status register write disable (srwd) bit in accordance with the write protect (w /v pp ) signal. the status register write disable (srwd) bit and write protect (w /v pp ) signal allow the device to be put in the hardware protected mode (hpm). the write status register (wrsr) instruction is not executed once the hardware protected mode (hpm) is entered. figure 13. write status register (wrsr) instruction sequence c dq0 ai13735 s dq1 2 1 3456789101112131415 high impedance instruction status register in 0 765432 0 1 msb
m25px64 instructions 35/70 the protection features of the device are summarized in ta bl e 8 . when the status register write disable (srwd) bit of the status register is 0 (its initial delivery state), it is possible to write to the status register provided that the write enable latch (wel) bit has previously been set by a write enable (wren) instruction, regardless of the whether write protect (w /v pp ) is driven high or low. when the status register write disable (srwd) bit of the status register is set to ?1?, two cases need to be considered, depending on the state of write protect (w /v pp ): ? if write protect (w /v pp ) is driven high, it is possible to write to the status register provided that the write enable latch (wel) bit has previously been set by a write enable (wren) instruction. ? if write protect (w /v pp ) is driven low, it is not possible to write to the status register even if the write enable latch (wel) bit has previously been set by a write enable (wren) instruction (attempts to write to the status register are rejected, and are not accepted for execution). as a consequence, all the data bytes in the memory area that are software protected (spm) by the block protect (bp2, bp1, bp0) bits of the status register, are also hardware protected against data modification. regardless of the order of the two events, the hardware protected mode (hpm) can be entered: ? by setting the status register write disable (srwd) bit after driving write protect (w /v pp ) low ? or by driving write protect (w /v pp ) low after setting the status register write disable (srwd) bit. the only way to exit the hardware protected mode (hpm) once entered is to pull write protect (w /v pp ) high. if write protect (w /v pp ) is permanently tied high, the hardware protected mode (hpm) can never be activated, and only the software protected mode (spm), using the block protect (bp2, bp1, bp0) bits of the status register, can be used. table 8. protection modes w /v pp signal srwd bit mode write protection of the status register memory content protected area (1) 1. as defined by the values in the bl ock protect (bp2, bp1, bp0) bits of the status register, as shown in table 3 . unprotected area (1) 10 software protected (spm) status register is writable (if the wren instruction has set the wel bit) the values in the srwd, bp2, bp1 and bp0 bits can be changed protected against page program, sector erase and bulk erase ready to accept page program and sector erase instructions 00 11 01 hardware protected (hpm) status register is hardware write protected the values in the srwd, bp2, bp1 and bp0 bits cannot be changed protected against page program, sector erase and bulk erase ready to accept page program and sector erase instructions
instructions m25px64 36/70 6.6 read data bytes (read) the device is first selected by driving chip select (s ) low. the instruction code for the read data bytes (read) instruction is followed by a 3-byte address (a23-a0), each bit being latched-in during the rising edge of serial clock (c). then the memory contents, at that address, is shifted out on serial data output (dq1), each bit being shifted out, at a maximum frequency f r , during the falling edge of serial clock (c). the instruction sequence is shown in figure 14 . the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shifted out. the whole memory can, therefore, be read with a single read data bytes (read) instruction. when the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. the read data bytes (read) instruction is terminated by driving chip select (s ) high. chip select (s ) can be driven high at any time during data output. any read data bytes (read) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. figure 14. read data bytes (read) instruction sequence and data-out sequence 1. address bit a23 is don?t care. c dq0 ai13736b s dq1 23 2 1 345678910 2829303132333435 2221 3210 36 37 38 76543 1 7 0 high impedance data out 1 instruction 24-bit address (1) 0 msb msb 2 39 data out 2
m25px64 instructions 37/70 6.7 read data bytes at higher speed (fast_read) the device is first selected by driving chip select (s ) low. the instruction code for the read data bytes at higher speed (fast_read) instruction is followed by a 3-byte address (a23- a0) and a dummy byte, each bit being latched-in during the rising edge of serial clock (c). then the memory contents, at that address, are shifted out on serial data output (dq1) at a maximum frequency f c , during the falling edge of serial clock (c). the instruction sequence is shown in figure 15 . the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shifted out. the whole memory can, therefore, be read with a single read data bytes at higher speed (fast_read) instruction. when the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. the read data bytes at higher speed (fast_read) instruction is terminated by driving chip select (s ) high. chip select (s ) can be driven high at any time during data output. any read data bytes at higher speed (fast_read) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. figure 15. read data bytes at higher speed (fast_read) instruction sequence and data-out sequence 1. address bit a23 is don?t care. c dq0 ai13737b s dq1 23 2 1 345678910 28293031 2221 3210 high impedance instruction 24-bit address (1) 0 c dq0 s dq1 32 33 34 36 37 38 39 40 41 42 43 44 45 46 765432 0 1 data out 1 dummy byte msb 7 6543210 data out 2 msb msb 7 47 765432 0 1 35
instructions m25px64 38/70 6.8 dual output fast read (dofr) the dual output fast read (dofr) instruction is very similar to the read data bytes at higher speed (fast_read) instruction, except that the data are shifted out on two pins (pin dq0 and pin dq1) instead of only one. outputting the data on two pins instead of one doubles the data transfer bandwidth compared to the read data bytes at higher speed (fast_read) instruction. the device is first selected by driving chip select (s ) low. the instruction code for the dual output fast read instruction is followed by a 3-byte address (a23-a0) and a dummy byte, each bit being latched-in during the rising edge of serial clock (c). then the memory contents, at that address, are shifted out on dq0 and dq1 at a maximum frequency f c , during the falling edge of serial clock (c). the instruction sequence is shown in figure 16 . the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shifted out on dq0 and dq1. the whole memory can, therefore, be read with a single dual output fast read (dofr) instruction. when the highest address is reached, the address counter rolls over to 00 0000h, so that the read sequence can be continued indefinitely. figure 16. dual output fast read instruction sequence 1. address bit a23 is don?t care. 2 1 345678910 28293031 0 23 22 21 3 2 1 0 mode 3 mode 2 c dq0 s dq1 high impedance instruction 24-bit address (1) c dq0 s dq1 32 33 34 36 37 38 39 40 41 42 43 44 45 46 753175 1 3 data out 1 dummy byte msb 7 531 7531 msb msb 47 6420 64 0 2 35 642064 0 2 msb msb data out 2 data out 3 data out n ai13574b
m25px64 instructions 39/70 6.9 read lock register (rdlr) the device is first selected by driving chip select (s ) low. the instruction code for the read lock register (rdlr) instruction is followed by a 3-byte address (a23-a0) pointing to any location inside the concerned sector. each address bit is latched-in during the rising edge of serial clock (c). then the value of the lock register is shifted out on serial data output (dq1), each bit being shifted out, at a maximum frequency f c , during the falling edge of serial clock (c). the instruction sequence is shown in figure 17 . the read lock register (rdlr) instruction is terminated by driving chip select (s ) high at any time during data output. any read lock register (rdlr) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. figure 17. read lock register (rdlr) instruction sequence and data-out sequence table 9. lock register out (1) 1. values of (b1, b0) after power-up are defined in section 7: power-up and power-down . bit bit name value function b7-b2 reserved b1 sector lock down ?1? the write lock and lock down bits cannot be changed. once a ?1? is written to the lock down bit it cannot be cleared to ?0?, except by a power-up. ?0? the write lock and lock down bits can be changed by writing new values to them. b0 sector write lock ?1? write, program and erase operations in this sector will not be executed. the memory contents will not be changed. ?0? write, program and erase operations in this sector are executed and will modify the sector contents. c d q0 ai13738 s dq1 23 2 1 345678910 2829303132333435 2221 3210 36 37 38 76543 1 0 high impedance lock register out instruction 24-bit address 0 msb msb 2 39
instructions m25px64 40/70 6.10 read otp (rotp) the device is first selected by driving chip select (s ) low. the instruction code for the read otp (rotp) instruction is followed by a 3-byte address (a23- a0) and a dummy byte. each bit is latched in on the rising edge of serial clock (c). then the memory contents at that address are shifted out on serial data output (dq1). each bit is shifted out at the maximum frequency, f c max, on the falling edge of serial clock (c). the instruction sequence is shown in figure 18 . the address is automatically incremented to the next higher address after each byte of data is shifted out. there is no rollover mechanism with the read otp (rotp) instruction. this means that the read otp (rotp) instruction must be sent with a maximum of 65 bytes to read, since once the 65th byte has been read, the same (65th) byte keeps being read on the dq1 pin. the read otp (rotp) instruction is terminated by driving chip select (s ) high. chip select (s ) can be driven high at any time during data output. any read otp (rotp) instruction issued while an erase, program or write cycle is in progress, is rejected without having any effect on the cycle that is in progress. figure 18. read otp (rotp) instruction and data-out sequence 1. a23 to a7 are don't care. 2. 1 n 65. c dq0 ai13573 s dq1 23 2 1 345678910 28293031 2221 3210 high impedance instruction 24-bit address 0 c dq0 s dq1 32 33 34 36 37 38 39 40 41 42 43 44 45 46 765432 0 1 data out 1 dummy byte msb 7 6543210 data out n msb msb 7 47 765432 0 1 35
m25px64 instructions 41/70 6.11 page program (pp) the page program (pp) instruction allows bytes to be programmed in the memory (changing bits from ?1? to ?0?). before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been decoded, the device sets the write enable latch (wel). the page program (pp) instruction is entered by driving chip select (s ) low, followed by the instruction code, three address bytes and at least one data byte on serial data input (dq0). if the 8 least significant address bits (a7-a0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits (a7-a0) are all zero). chip select (s ) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 19 . if more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. if less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. for optimized timings, it is recommended to use the page program (pp) instruction to program all consecutive targeted bytes in a single sequence versus using several page program (pp) sequences with each containing only a few bytes (see table 18: ac characteristics ). chip select (s ) must be driven high after the eighth bit of the last data byte has been latched in, otherwise the page program (pp) instruction is not executed. as soon as chip select (s ) is driven high, the self-timed page program cycle (whose duration is t pp ) is initiated. while the page program cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed page program cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. a page program (pp) instruction applied to a page which is protected by the block protect (bp2, bp1, bp0) bits (see table 3 and ta bl e 4 ) is not executed.
instructions m25px64 42/70 figure 19. page program (pp) instruction sequence 1. address bit a23 is don?t care. c dq0 ai13739b s 42 41 43 44 45 46 47 48 49 50 52 53 54 55 40 c dq0 s 23 2 1 345678910 2829303132333435 2221 3210 36 37 38 instruction 24-bit address (1) 0 765432 0 1 data byte 1 39 51 765432 0 1 data byte 2 765432 0 1 data byte 3 data byte 256 2079 2078 2077 2076 2075 2074 2073 765432 0 1 2072 msb msb msb msb msb
m25px64 instructions 43/70 6.12 dual input fast program (difp) the dual input fast program (difp) instruction is very similar to the page program (pp) instruction, except that the data are entered on two pins (pin dq0 and pin dq1) instead of only one. inputting the data on two pins instead of one doubles the data transfer bandwidth compared to the page program (pp) instruction. the dual input fast program (difp) instruction is entered by driving chip select (s ) low, followed by the instruction code, three address bytes and at least one data byte on serial data input (dq0). if the 8 least significant address bits (a7-a0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits (a7-a0) are all zero). chip select (s ) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 20 . if more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. if less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes in the same page. for optimized timings, it is recommended to use the dual input fast program (difp) instruction to program all consecutive targeted bytes in a single sequence rather to using several dual input fast program (difp) sequences each containing only a few bytes (see table 18: ac characteristics ). chip select (s ) must be driven high after the eighth bit of the last data byte has been latched in, otherwise the dual input fast program (difp) instruction is not executed. as soon as chip select (s ) is driven high, the self-timed page program cycle (whose duration is t pp ) is initiated. while the dual input fast program (difp) cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed page program cycle, and 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. a dual input fast program (difp) instruction applied to a page that is protected by the block protect (bp2, bp1, bp0) bits (see ta bl e 2 and table 3 ) is not executed.
instructions m25px64 44/70 figure 20. dual input fast program (difp) instruction sequence 1. address bit a23 is don?t care. ai14229 c dq0 s 2 1 345678910 28293031 22 21 3 2 1 0 instruction 24-bit address 0 c dq0 s 34 33 35 36 37 38 39 40 41 42 44 45 46 47 32 43 642064 0 2 642064 0 2 6420 msb msb msb dq1 high impedance 64 2 0 dq1 7531 1 75 3 75 3 7 5 msb 31 1 msb 7531 75 3 1 msb data in 1 data in 4 data in 5 data in 256 data in 3 data in 2 23
m25px64 instructions 45/70 6.13 program otp instruction (potp) the program otp instruction (potp) is used to program at most 64 bytes to the otp memory area (by changing bits from ?1? to ?0?, only). before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been decoded, the device sets the write enable latch (wel) bit. the program otp instruction is entered by driving chip select (s ) low, followed by the instruction opcode, three address bytes and at least one data byte on serial data input (dq0). chip select (s ) must be driven high after the eighth bit of the last data byte has been latched in, otherwise the program otp instruction is not executed. there is no rollover mechanism with the program otp (potp) instruction. this means that the program otp (potp) instruction must be sent with a maximum of 65 bytes to program, once all 65 bytes have been latched in, any following byte will be discarded. the instruction sequence is shown in figure 21 . as soon as chip select (s ) is driven high, the self-timed page program cycle (whose duration is t pp ) is initiated. while the program otp cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed program otp cycle, and it is 0 when it is completed. at some unspecified time before the cycle is complete, the write enable latch (wel) bit is reset. to lock the otp memory: bit 0 of the otp control byte, that is byte 64, (see figure 22 ) is used to permanently lock the otp memory array. ? when bit 0 of byte 64 = ?1?, the 64 bytes of the otp memory array can be programmed. ? when bit 0 of byte 64 = ?0?, the 64 bytes of the otp memory array are read-only and cannot be programmed anymore. once a bit of the otp memory has been programmed to ?0?, it can no longer be set to ?1?. therefore, as soon as bit 0 of byte 64 (control byte) is set to ?0?, the 64 bytes of the otp memory array become read-only in a permanent way. any program otp (potp) instruction issued while an erase, program or write cycle is in progress is rejected without having any effect on the cycle that is in progress.
instructions m25px64 46/70 figure 21. program otp (potp) instruction sequence 1. a23 to a7 are don't care. 2. 1 n 65. figure 22. how to permanently lock the 64 otp bytes c dq0 ai13575 s 42 41 43 44 45 46 47 48 49 50 52 53 54 55 40 c dq0 s 23 2 1 345678910 2829303132333435 2221 3210 36 37 38 instruction 24-bit address 0 765432 0 1 data byte 1 39 51 765432 0 1 data byte 2 765432 0 1 data byte 3 data byte n 765432 0 1 msb msb msb msb msb byte 0 byte 1 byte 2 byte 64 byte 63 x x x x x x x bit 0 otp control byte 64 data bytes bit 1 to bit 7 are not programmable when bit 0 = 0 the 64 otp bytes become read only ai13587
m25px64 instructions 47/70 6.14 write to lock register (wrlr) the write to lock register (wrlr) instruction allows bits to be changed in the lock registers. before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been decoded, the device sets the write enable latch (wel). the write to lock register (wrlr) instruction is entered by driving chip select (s ) low, followed by the instruction code, three address bytes (pointing to any address in the targeted sector and one data byte on serial data input (dq0). the instruction sequence is shown in figure 23 . chip select (s ) must be driven high after the eighth bit of the data byte has been latched in, otherwise the write to lock register (wrlr) instruction is not executed. lock register bits are volatile, and therefore do not require time to be written. when the write to lock register (wrlr) instruction has been successfully executed, the write enable latch (wel) bit is reset after a delay time less than t shsl minimum value. any write to lock register (wrlr) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. figure 23. write to lock register (wrlr) instruction sequence table 10. lock register in (1) 1. values of (b1, b0) after power-up are defined in section 7: power-up and power-down . sector bit value all sectors b7-b2 ?0? b1 sector lock down bit value (refer to ta ble 9 ) b0 sector write lock bit value (refer to tab le 9 ) ai13740 c dq0 s 23 2 1 345678910 2829303132333435 2221 3210 36 37 38 instruction 24-bit address 0 765432 0 1 lock register in 39 msb msb
instructions m25px64 48/70 6.15 subsector erase (sse) the subsector erase (sse) instruction sets to ?1? (ffh) all bits inside the chosen subsector. before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been decoded, the device sets the write enable latch (wel). the subsector erase (sse) instruction is entered by driving chip select (s ) low, followed by the instruction code, and three address bytes on serial data input (dq0). any address inside the subsector (see table 4 ) is a valid address for the subsector erase (sse) instruction. chip select (s ) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 24 . chip select (s ) must be driven high after the eighth bit of the last address byte has been latched in, otherwise the subsector erase (sse) instruction is not executed. as soon as chip select (s ) is driven high, the self-timed subsector erase cycle (whose duration is t sse ) is initiated. while the subsector erase cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed subsector erase cycle, and is 0 when it is completed. at some unspecified time before the cycle is complete, the write enable latch (wel) bit is reset. a subsector erase (sse) instruction issued to a sector that is hardware or software protected, is not executed. any subsector erase (sse) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. figure 24. subsector erase ( sse) instruction sequence 1. address bit a23 is don?t care. 24-bit address (1) c dq0 ai13741b s 2 1 3456789 293031 instruction 0 23 22 20 1 msb
m25px64 instructions 49/70 6.16 sector erase (se) the sector erase (se) instruction sets to ?1? (ffh) all bits inside the chosen sector. before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been decoded, the device sets the write enable latch (wel). the sector erase (se) instruction is entered by driving chip select (s ) low, followed by the instruction code, and three address bytes on serial data input (dq0). any address inside the sector (see ta bl e 4 ) is a valid address for the sector erase (se) instruction. chip select (s ) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 25 . chip select (s ) must be driven high after the eighth bit of the last address byte has been latched in, otherwise the sector erase (se) instruction is not executed. as soon as chip select (s ) is driven high, the self-timed sector erase cycle (whose duration is t se ) is initiated. while the sector erase cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed sector erase cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. a sector erase (se) instruction applied to a page which is protected by the block protect (bp2, bp1, bp0) bits (see table 3 and ta bl e 4 ) is not executed. figure 25. sector erase (se) instruction sequence 1. address bit a23 is don?t care. 24-bit address (1) c dq1 ai13742b s 2 1 3456789 293031 instruction 0 23 22 2 0 1 msb
instructions m25px64 50/70 6.17 bulk erase (be) the bulk erase (be) instruction sets all bits to ?1? (ffh). before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been decoded, the device sets the write enable latch (wel). the bulk erase (be) instruction is entered by driving chip select (s ) low, followed by the instruction code on serial data input (dq0). chip select (s ) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 26 . chip select (s ) must be driven high after the eighth bit of the instruction code has been latched in, otherwise the bulk erase instruction is not executed. as soon as chip select (s ) is driven high, the self-timed bulk erase cycle (whose duration is t be ) is initiated. while the bulk erase cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed bulk erase cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. the bulk erase (be) instruction is executed only if all block protect (bp2, bp1, bp0) bits are 0. the bulk erase (be) instruction is ignored if one, or more, sectors are protected. figure 26. bulk erase (be) instruction sequence c dq0 ai13743 s 2 1 34567 0 instruction
m25px64 instructions 51/70 6.18 deep power-down (dp) executing the deep power-down (dp) instruction is the only way to put the device in the lowest consumption mode (the deep power-down mode). it can also be used as a software protection mechanism, while the device is not in active use, as in this mode, the device ignores all write, program and erase instructions. driving chip select (s ) high deselects the device, and puts the device in the standby power mode (if there is no internal cycle currently in progress). but this mode is not the deep power-down mode. the deep power-down mode can only be entered by executing the deep power-down (dp) instruction, subsequently reducing the standby current (from i cc1 to i cc2 , as specified in table 17 ). to take the device out of deep power-down mode, the release from deep power-down (rdp) instruction must be issued. no other instruction must be issued while the device is in deep power-down mode. the deep power-down mode automatically stops at power-down, and the device always powers up in the standby power mode. the deep power-down (dp) instruction is entered by driving chip select (s ) low, followed by the instruction code on serial data input (dq0). chip select (s ) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 27 . chip select (s ) must be driven high after the eighth bit of the instruction code has been latched in, otherwise the deep power-down (dp) instruction is not executed. as soon as chip select (s ) is driven high, it requires a delay of t dp before the supply current is reduced to i cc2 and the deep power-down mode is entered. any deep power-down (dp) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. figure 27. deep power-down (dp) instruction sequence c dq0 ai13744 s 2 1 34567 0 t dp deep power-down mode standby mode instruction
instructions m25px64 52/70 6.19 release from deep power-down (rdp) once the device has entered the deep power-down mode, all instructions are ignored except the release from deep power-down (rdp) instruction. executing this instruction takes the device out of the deep power-down mode. the release from deep power-down (rdp) instruction is entered by driving chip select (s ) low, followed by the instruction code on serial data input (dq0). chip select (s ) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 28 . the release from deep power-down (rdp) instruction is terminated by driving chip select (s ) high. sending additional clock cycles on serial clock (c), while chip select (s ) is driven low, cause the instruction to be rejected, and not executed. after chip select (s ) has been driven high, followed by a delay, t rdp , the device is put in the standby mode. chip select (s ) must remain high at least until this period is over. the device waits to be selected, so that it can receive, decode and execute instructions. any release from deep power-down (rdp) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. figure 28. release from deep power-down (rdp) instruction sequence c dq0 ai13745 s 2 1 34567 0 t rdp standby mode deep power-down mode dq1 high impedance instruction
m25px64 power-up and power-down 53/70 7 power-up and power-down at power-up and power-down, the device must not be selected (that is chip select (s ) must follow the voltage applied on v cc ) until v cc reaches the correct value: ? v cc (min) at power-up, and then for a further delay of t vsl ? v ss at power-down. a safe configuration is provided in section 3: spi modes . to avoid data corruption and inadvertent write operations during power-up, a power on reset (por) circuit is included. the logic inside the device is held reset while v cc is less than the power on reset (por) threshold voltage, v wi ? all operations are disabled, and the device does not respond to any instruction. moreover, the device ignores all write enable (wren), page program (pp), dual input fast program (difp), program otp (potp), subsector erase (sse), sector erase (se), bulk erase (be), write status register (wrsr) and write to lock register (wrlr) instructions until a time delay of t puw has elapsed after the moment that v cc rises above the v wi threshold. however, the correct operation of the device is not guaranteed if, by this time, v cc is still below v cc (min). no write status register, program or erase instructions should be sent until the later of: ? t puw after v cc has passed the v wi threshold ? t vsl after v cc has passed the v cc (min) level. these values are specified in table 11 . if the time, t vsl , has elapsed, after v cc rises above v cc (min), the device can be selected for read instructions even if the t puw delay has not yet fully elapsed. after power-up, the device is in the following state: ? the device is in the standby power mode (not the deep power-down mode) ? the write enable latch (wel) bit is reset ? the write in progress (wip) bit is reset ? the lock registers are configured as: (write lock bit, lock down bit) = (0,0). normal precautions must be taken for supply line decoupling, to stabilize the v cc supply. each device in a system should have the v cc line decoupled by a suitable capacitor close to the package pins (generally, this capacitor is of the order of 100 nf). at power-down, when v cc drops from the operating voltage, to below the power on reset (por) threshold voltage, v wi , all operations are disabled and the device does not respond to any instruction (the designer needs to be aware that if power-down occurs while a write, program or erase cycle is in progress, some data corruption may result). ? v pph must be applied only when v cc is stable and in the v cc (min) to v cc (max) voltage range.
initial delivery state m25px64 54/70 figure 29. power-up timing 8 initial delivery state the device is delivered with the memory array erased: all bits are set to ?1? (each byte contains ffh). the status register contains 00h (all status register bits are 0). table 11. power-up timing and v wi threshold symbol parameter min max unit t vsl (1) 1. these parameters are characterized only. v cc (min) to s low 30 s t puw (1) time delay to write instruction 1 10 ms v wi (1) write inhibit voltage 1.5 2.5 v v cc ai04009c v cc (min) v wi reset state of the device chip selection not allowed program, erase and write commands are rejected by the device tvsl tpuw tim e read access allowed device fully accessible v cc (max)
m25px64 maximum ratings 55/70 9 maximum ratings stressing the device outside the ratings listed in table 12: absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the numonyx sure program and other relevant quality documents. table 12. absolute maximum ratings symbol parameter min max unit t stg storage temperature ?65 150 c t lead lead temperature during soldering see (1) 1. compliant with jedec std j-std-020c (for small body, sn-pb or pb assembly), and the european directive on restrictions on hazardous substances (rohs) 2002/95/eu. c v io input and output voltage (with respect to ground) ?0.6 v cc +0.6 v v cc supply voltage ?0.6 4.0 v v pp fast program/erase voltage (2) 2. avoid applying v pph to the w /vpp pin during bulk erase. ?0.2 10.0 v v esd electrostatic discharge voltage (human body model) (3) 3. jedec std jesd22-a114a (c1 = 100 pf, r1 = 1500 , r2 = 500 ). ?2000 2000 v
dc and ac parameters m25px64 56/70 10 dc and ac parameters this section summarizes the operating and measurement conditions, and the dc and ac characteristics of the device. the parameters in the dc and ac characteristics tables that follow are derived from tests performed under the measurement conditions summarized in the relevant tables. designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. table 14. data retention and endurance figure 30. ac measurement i/o waveform table 13. operating conditions symbol parameter min typ max unit vcc supply voltage 2.7 3.6 v vphh supply voltage on vpp 8.5 9.5 v ta ambient operating temperature (device grade 6) -40 85 c ambient operating temperature (device grade 3) -40 125 parameter condition min. max. unit program/erase cycles grade 3, autograde 6, grade 6 100000 cycles per sector data retention at 55c 20 years table 15. ac measurement conditions symbol parameter min max unit c l load capacitance 30 pf input rise and fall times 5 ns input pulse voltages 0.2v cc to 0.8v cc v input timing reference voltages 0.3v cc to 0.7v cc v output timing reference voltages v cc / 2 v ai07455 0.8v cc 0.2v cc 0.7v cc 0.3v cc input and output timing reference levels input levels 0.5v cc
m25px64 dc and ac parameters 57/70 table 16. capacitance (1) 1. sampled only, not 100% tested, at t a =25 c and a frequency of 33 mhz. symbol parameter test condition min max unit c in/out input/output capacitance (dq0/dq1) v out = 0 v 8 pf c in input capacitance (other pins) v in = 0 v 6 pf table 17. dc characteristics symbol parameter test condition (in addition to those in table 13 ) min max unit i li input leakage current 2 a i lo output leakage current 2 a i cc1 standby current s = v cc , v in = v ss or v cc 50 a i cc2 deep power-down current s = v cc , v in = v ss or v cc 10 a i cc3 operating current (read) c = 0.1v cc / 0.9v cc at 75 mhz, dq1 = open 12 ma c = 0.1v cc / 0.9v cc at 33 mhz, dq1 = open 4ma operating current (dofr) c = 0.1v cc / 0.9v cc at 75 mhz, dq1 = open 15 ma i cc4 operating current (pp) s = v cc 15 ma operating current (difp) s = v cc 15 ma i cc5 operating current (wrsr) s = v cc 15 ma i cc6 operating current (se) s = v cc 15 ma v il input low voltage ? 0.5 0.3v cc v v ih input high voltage 0.7v cc v cc +0.4 v v ol output low voltage i ol = 1.6 ma 0.4 v v oh output high voltage i oh = ?100 av cc ?0.2 v
dc and ac parameters m25px64 58/70 table 18. ac characteristics test conditions specified in table 13 and table 15 symbol alt. parameter min typ (1) max unit f c f c clock frequency for the following instructions: dofr, difp, fast_read, sse, se, be, dp, wren, wrdi, rdid, rdsr, wrsr, rotp, pp, potp, wrlr, rdlr, rdp d.c. 75 mhz f r clock frequency for read instructions d.c. 33 mhz t ch (2) t clh clock high time 6 ns t cl (2) t cll clock low time 6 ns t clch (3) clock rise time (4) (peak to peak) 0.1 v/ns t chcl (3) clock fall time (4) (peak to peak) 0.1 v/ns t slch t css s active setup time (relative to c) 5 ns t chsl s not active hold time (relative to c) 5 ns t dvch t dsu data in setup time 2 ns t chdx t dh data in hold time 5 ns t chsh s active hold time (relative to c) 5 ns t shch s not active setup time (relative to c) 5 ns t shsl t csh s deselect time 80 ns t shqz (3) t dis output disable time 8 ns t clqv t v clock low to output valid under 30 pf 8 ns clock low to output valid under 10 pf 6 ns t clqx t ho output hold time 0 ns t hlch hold setup time (relative to c) 5 ns t chhh hold hold time (relative to c) 5 ns t hhch hold setup time (relative to c) 5 ns t chhl hold hold time (relative to c) 5 ns t hhqx (3) t lz hold to output low-z 8 ns t hlqz (3) t hz hold to output high-z 8 ns t whsl (5) write protect setup time 20 ns t shwl (5) write protect hold time 100 ns t vpphsl (6) enhanced program supply voltage high (v pph ) to chip select low 200 ns t dp (3) s high to deep power-down mode 3 s t rdp (3) s high to standby mode 30 s
m25px64 dc and ac parameters 59/70 figure 31. serial input timing t w write status register cycle time 1.3 15 ms t pp (7) page program cycle time (256 bytes) 0.8 5 ms page program cycle time (n bytes) int(n/8) 0.025 (8) program otp cycle time (64 bytes) 0.2 ms t sse subsector erase cycle time 70 150 ms t se sector erase cycle time 0.7 3 s t be bulk erase cycle time 68 160 s 1. typical values given for t a = 25 c. 2. t ch + t cl must be greater than or equal to 1/ f c . 3. value guaranteed by characterization, not 100% tested in production. 4. expressed as a slew-rate. 5. only applicable as a constraint for a wrsr instruction when srwd is set to ?1?. 6. v pph should be kept at a valid level until the program or erase operation has completed and its result (success or failure) is known. avoid applying v pph to the w /vpp pin during bulk erase. 7. when using the page program (pp) instruction to pr ogram consecutive bytes, optimized timings are obtained with one sequence including all the bytes versus several sequences of only a few bytes (1 n 256). 8. int(a) corresponds to the upper integer part of a. fo r example int(12/8) = 2, int(32/8) = 4 int(15.3) =16. table 18. ac characteristics (continued) test conditions specified in table 13 and table 15 symbol alt. parameter min typ (1) max unit c dq0 ai13728 s msb in dq1 tdvch high impedance lsb in tslch tchdx tchcl tclch tshch tshsl tchsh tchsl
dc and ac parameters m25px64 60/70 figure 32. write protect setup and hold timing during wrsr when srwd=1 figure 33. hold timing c dq0 s dq1 high impedance w/v pp twhsl tshwl ai07439c c dq1 ai13746 s dq0 hold tchhl thlch thhch tchhh thhqx thlqz
m25px64 dc and ac parameters 61/70 figure 34. output timing figure 35. v pph timing c dq1 ai13729 s lsb out dq0 addr. lsb in tshqz tch tcl tqlqh tqhql tclqx tclqv tclqx tclqv s c dq0 v pp v pph ai13726-b tvpphsl end of command (identified by wip polling)
package mechanical m25px64 62/70 11 package mechanical in order to meet environmental requirements, numonyx offers these devices in rohs packages. these packages have a lead-free second level interconnect. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. figure 36. vdfpn8 (mlp8, me) 8-lead very thin dual flat package no lead, 8 6 mm, package outline 1. drawing is not to scale. 2. the circle in the top view of the package indicates the position of pin 1. table 19. vdfpn8 (mlp8, me) 8-lead very thin dual flat package no lead, 8 6 mm, package mechanical data symbol millimeters inches typ min max typ min max a 0.85 1.00 0.033 0.039 a1 0.00 0.05 0.000 0.002 b 0.40 0.35 0.48 0.016 0.014 0.019 d 8.00 0.315 d2 5.16 (1) 1. d2 max must not exceed (d ? 2 x k ? 2 l). 0.203 ddd 0.05 0.002 e 6.00 0.236 e2 4.80 0.189 e 1.27 ? ? 0.050 ? ? k0.82 0.032 l 0.50 0.45 0.60 0.020 0.018 0.024 l1 0.15 0.006 n8 8 d e vdfpn-02 a e e2 d2 l b l1 a1 ddd k
m25px64 package mechanical 63/70 figure 37. vdfpn8 (mlp8, md) 8-lead very thin dual flat package no lead, 8 6 mm, package outline 1. drawing is not to scale. 2. the circle in the top view of the package indicates the position of pin 1. table 20. vdfpn8 (mlp8, md) 8-lead very thin dual flat package no lead, 8 6 mm, package mechanical data symbol millimeters inches typ min max typ min max a 0.85 1.00 0.033 0.039 a1 0.00 0.05 0.000 0.002 b 0.40 0.35 0.48 0.016 0.014 0.019 d 8.00 0.315 d2 4.70 4.725 0.187 ddd 0.05 0.002 e 6.00 0.236 e2 4.80 0.189 e 1.27 ? ? 0.050 ? ? k1.05 0.032 l 0.50 0.45 0.60 0.020 0.018 0.024 l1 0.15 0.006 n8 8 d e vdfpn-02 a e e2 d2 l b l1 a1 ddd k
package mechanical m25px64 64/70 figure 38. so16 wide - 16-lead plastic small outline, 300 mils body width, package outline 1. drawing is not to scale. table 21. so16 wide - 16-lead plastic small outline, 300 mils body width, mechanical data symbol millimeters inches typ min max typ min max a 2.35 2.65 0.093 0.104 a1 0.10 0.30 0.004 0.012 b 0.33 0.51 0.013 0.020 c 0.23 0.32 0.009 0.013 d 10.10 10.50 0.398 0.413 e 7.40 7.60 0.291 0.299 e 1.27 ? ? 0.050 ? ? h 10.00 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 l 0.40 1.27 0.016 0.050 0 8 0 8 ddd 0.10 0.004 e 16 d c h 1 8 9 so-h l a1 a ddd a2 b e h x 45?
m25px64 package mechanical 65/70 figure 39. tbga, 6x8 mm, 24 ball package outline
package mechanical m25px64 66/70 table 22. tbga 6x8 mm 24-ball package dimensions min nom max a1.20 a1 0.20 a2 0.79 ?b 0.35 0.40 0.45 d 5.90 6.00 6.10 d1 4.00 e 7.90 8.00 8.10 e1 4.00 ed 1.00 ee 1.00 fd 1.00 fe 2.00 md 5 me 5 n 24 balls aaa 0.15 bbb 0.10 ddd 0.10 eee 0.15 fff 0.08 control unit: mm
m25px64 ordering information 67/70 12 ordering information table 23. ordering information scheme example: m25px64 ? v me 3 t p b a device type m25px = serial flash memory, 4-kbyte and 64-kbyte erasable sectors, dual input/output device function 64 = 64 mbit (8 mb 8) security features (1) ? = no extra security so = otp configurable + cfd programmed with uid st = otp configurable + protection at power_up + cfd programmed with uid s? = cfd programmed with uid operating voltage v = v cc = 2.7v to 3.6v package me = vdfpn8 8 6 mm (mlp8) mf = so16 (300 mils width) zm = tbga24 6 x 8 mm md = vdfpn8 8 6 mm (mlp8), with reduced d2 dimension device grade 6 = industrial temperature range, ?40 to 85 c. device tested with standard test flow 3 (2) = automotive temperature range, ?40 to 125 c. device tested with high reliability certified flow (3) . option blank = standard packing t = tape and reel packing plating technology p or g = rohs compliant lithography b = 110nm, fab.2 diffusion plant blank = 110 nm automotive grade a (2) = automotive ?40 to 125 c part. device tested with high reliability certified flow. (3) blank = standard ?40 to 85 c device 1. secure options are available upon customer request.
ordering information m25px64 68/70 note: for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest numonyx sales office. 2. numonyx strongly recommends the use of the automotive grade devices(autograde 6 and grade 3) for use in an automotive environment. the high reliability certified flow (hrcf) is described in the quality note qnee9801. 3. device grade 3 available in an so8 rohs compliant package.
m25px64 revision history 69/70 13 revision history table 24. document revision history date revision changes 05-nov-2007 1 initial release. 25-mar-2008 2 updated the minimum value for t shsl in table 18: ac characteristics . applied numonyx branding. 24-sept-2008 3 corrected bulk erase specifications on the cover page. added the following information regarding bulk erase: avoid applying v pph to the w /vpp pin during bulk erase. 04-february-2009 4 added the tbga package and accompanying informaiton. 16-february-2009 5 added notes to the tbga package and deleted a blank page. 6-march-2009 6 added ?automotive certified parts? information. 22-may-2009 7 removed ipp from table 17: dc characteristics . 22-september-2009 8 added vdpn8 (md) 8 x 6 (mlp8) package information 8-october-2009 9 revised table 19.: vdfpn8 (mlp8, me) 8-lead very thin dual flat package no lead, 8 6 mm, package mechanical data as follows: ? footnote changed from d2 max must not exceed (d ? k ? 2 l) to d2 max must not exceed (d ? 2 x k ? 2 l) revised table 20.: vdfpn8 (mlp8, md) 8-lead very thin dual flat package no lead, 8 6 mm, package mechanical data as follows: ? footnote changed from d2 max must not exceed (d ? k ? 2 l) to d2 max must not exceed (d ? 2 x k ? 2 l) ? changed d2 typ from 4.75 to 4.70 ? changed k min from 0.82 to 1.05 25-november-2009 10 revised table 20.: vdfpn8 (mlp8, md) 8-lead very thin dual flat package no lead, 8 6 mm, package mechanical data as follows: ? d2 max?note deleted and maximum value inserted instead.
m25px64 70/70 please read carefully: information in this document is provided in connection with numonyx? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in numonyx's terms and conditions of sale for such products, numonyx assumes no liability whatsoever, and numonyx disclaims any express or implied warranty, relating to sale and/or use of numonyx products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in n uclear facility applications. numonyx may make changes to specifications and product descriptions at any time, without notice. numonyx, b.v. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights th at relate to the presented subject matter. the furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. designers must not rely on the absence or characteristics of any features or instructions marked ?reserved? or ?undefined.? num onyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. contact your local numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. copies of documents which have an order number and are referenced in this document, or other numonyx literature may be obtained by visiting numonyx's website at http://www.numonyx.com . numonyx strataflash is a trademark or registered trademark of numonyx or its subsidiaries in the united states and other countr ies. *other names and brands may be claimed as the property of others. copyright ? 2009, numonyx b.v. all rights reserved.

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